1. Field of the Invention
The present invention relates to a microprocessor, and more particularly, relates to a pipeline processing-type microprocessor having a hard accelerator (a built-in accelerator).
2. Description of the Related Art
Recently, the performance of an electronic apparatus has been drastically enhanced and a demand for a microprocessor having throughput is increasing so as to be in charge of a control system of the electronic apparatus. On the other hand, in view of a travel time of a small, portable apparatus or an environmental problem, a microprocessor having low power consumption is demanded. In the development of the microprocessor, it is important to realize these contradictory demands in balance.
In order to efficiently use limited throughput of a processor core (CPU), a high-end microprocessor is provided with a built-in hard accelerator (including a co-processor) having functions implemented by hardware, which are generally implemented by software. In such a microprocessor, only a specific processing which can be performed by the hard accelerator can be performed at high speed with hardware by starting the hard accelerator, without operating the processor core. The processor core can execute additional processing during the execution of the processing by the hard accelerator.
Further, in Japanese Unexamined Patent Application Publication No. Sho 60-553, a technique which, in a channel-command-word-type system, can enhance an efficiency of an interrupt processing of a main central processing unit on the interrupt when a channel device generates an interrupt at the time of receiving data is disclosed. Specifically, a receive command completion bit is provided in an interrupt status register of the channel device. The main central processing unit checks the receive command completion bit when a channel command word completion interrupt is generated from the channel device and recognizes the completion of the receive command indicating the data reception of the channel device if the receive command completion bit is set.
When the specific processing is executed by the hard accelerator, the processor core needs to recognize whether or not the processing is completed by the hard accelerator. For this reason, the processor core needs to execute polling regularly for the hard accelerator or needs to wait for the generation of the interrupt indicating the processing completion of the hard accelerator. Thus, during the processing of the hard accelerator, the processor core needs to be operated constantly so as only to recognize the processing completion of the hard accelerator, even when there is no processing to be executed. As a result, useless power consumption occurs.
In order to solve this problem, when a processing-completion waiting operation mechanism to the hard accelerator is constructed, as the easiest unit, a dedicated circuit for executing a processing-completion waiting operation with respect to the hard accelerator is provided. Assuming that such a dedicated circuit is mounted on the microprocessor, examination of a circuit, which judges the processing status of the hard accelerator, is required independently of the processor core. On this circuit, a mechanism for starting the processor core changed over a low power consumption mode after the processing completion of the hard accelerator needs to be mounted. Thus, at the time of the design and development of the microprocessor with such a dedicated circuit mounted thereon, it is necessary to carefully examine a managing method of an interrupt generated during the low power consumption mode of the processor core or whether or not there occurs any problem in operations inherent in the microprocessor due to the mounting of the dedicated circuit. Further, after the design of the microprocessor is completed, new operation verification over multiple items is needed. In addition, with the mounting of the dedicated circuit, the circuit scale of the microprocessor may be increased.